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Enhanced Synchronous Serial Interface (ESSI)
Table 7-4. ESSI Control Register B (CRB) Bit Definitions (Continued)
Bit Number
14
Bit Name
TE2
Reset Value
0
Transmit 2 Enable
Description
Enables the transfer of data from TX2 to Transmit Shift Register 2. TE2 is
functional only when the ESSI is in Synchronous mode and is ignored when
the ESSI is in Asynchronous mode. When TE2 is set and a frame sync is
detected, transmitter 2 is enabled for that frame.
When TE2 is cleared, transmitter 2 is disabled after completing
transmission of data currently in the ESSI transmit shift register. Any data
present in TX2 is not transmitted. If TE2 is cleared, data can be written to
TX2; the TDE bit is cleared, but data is not transferred to transmit shift
register 2. If the TE2 bit is kept cleared until the start of the next frame, it
causes the SC1 signal to act as a serial I/O flag from the start of the frame
in both Normal mode and Network mode. The transmit enable sequence in
On-Demand mode can be the same as in Normal mode, or the TE2 bit can
be left enabled.
Note:
The setting of the TE2 bit does not affect the generation of frame
sync or output flags.
13
MOD
0
Mode Select
Selects the operational mode of the ESSI, as in Figure 7-8 on page -25,
Figure 7-9 on page -26, and Figure 7-10 on page -26. When MOD is
cleared, the Normal mode is selected; when MOD is set, the Network mode
is selected. In Normal mode, the frame rate divider determines the word
transfer rate: one word is transferred per frame sync during the frame sync
time slot. In Network mode, a word can be transferred every time slot. For
details, see Section 7.3 .
12
SYN
0
Synchronous/Asynchronous
Controls whether the receive and transmit functions of the ESSI occur
synchronously or asynchronously with respect to each other. (See Figure
7-7 on page -24.) When SYN is cleared, the ESSI is in Asynchronous
mode, and separate clock and frame sync signals are used for the transmit
and receive sections. When SYN is set, the ESSI is in Synchronous mode,
and the transmit and receive sections use common clock and frame sync
signals. Only in Synchronous mode can more than one transmitter be
enabled.
11
CKP
0
Clock Polarity
Controls which bit clock edge data and frame sync are clocked out and
latched in. If CKP is cleared, the data and the frame sync are clocked out
on the rising edge of the transmit bit clock and latched in on the falling edge
of the receive bit clock. If CKP is set, the data and the frame sync are
clocked out on the falling edge of the transmit bit clock and latched in on the
rising edge of the receive bit clock.
10
FSP
0
Frame Sync Polarity
Determines the polarity of the receive and transmit frame sync signals.
When FSP is cleared, the frame sync signal polarity is positive; that is, the
frame start is indicated by the frame sync signal going high. When FSP is
set, the frame sync signal polarity is negative; that is, the frame start is
indicated by the frame sync signal going low.
DSP56311 User’s Manual, Rev. 2
7-20
Freescale Semiconductor
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